In order to implement fault detection, some computer systems have two processors operated in strict cycle-by-cycle lock step. That is, each processor is provided duplicate copies of an instruction stream and substantially the same clock signal, and each processor performs identical operations within each cycle. When operating without error, each processor produces identical reads and/or writes in a clock cycle where those reads and/or writes are present. A hardware arbiter compares the reads and/or writes, and if identical the requests are allowed to advance to downstream hardware, such as a single shared main memory or an input/output (I/O) adapter. Faults, whether computational or transient, are detected as: timing differences (e.g., one processors presents a request earlier in time that a second processor); mismatched requests (e.g., one processor presents a read and the second processor presents a write); out of order request presentation (e.g., one processor presents a read followed by a write, and the second processor presents the same write, but first followed by the read); or by differences in read and/or write addresses and/or data. If a fault is detected, the requests are not forwarded to the downstream hardware.
Operating processors in strict cycle-by-cycle lock step assumes that each processor acts in exactly the same fashion when presented the same instruction stream and given the same clock signal. Stated otherwise, operating in strict cycle-by-cycle lock step assumes the processors behave deterministically. However, manufacturers now produce processors that, even if given the same instruction stream and the same clock signal, behave differently even when calculating the same results, and thus these processors are said to behave non-deterministically.